As materials used in semiconductor processes advance, line spacing and line widths of conductors formed by electrochemical plating (ECP) and chemical-mechanical polishing (CMP) are reduced. When material is formed by ECP and CMP to form conductors, problems such as gap filling, voids and pattern resolution (poor line quality) may occur.
To form conductive patterns on a semiconductor substrate using ECP, for each one of several metal layers to be formed over the semiconductor substrate, a dielectric layer is deposited over the semiconductor substrate. Using photolithography a conductor pattern for the selected metal layer is formed in a photoresist layer formed over the dielectric layer. An etch step is then performed on the underlying dielectric layer using the patterned photoresist as an etch mask to form patterned trenches. After the dielectric layer is etched, the photoresist is removed.
ECP may then be performed to deposit the conductive material into the trenches. In ECP, the substrate with the patterned dielectric layer is placed in an electrolyte electroplating bath solution, for example to electroplate copper conductors; the bath is acid copper sulfate solution. A sacrificial anode and the semiconductor substrate are immersed in the solution with the semiconductor substrate electrically coupled to act as a cathode. An electric potential is applied and the copper conductor material is drawn to the substrate by current flowing between the anode and the cathode terminals, and the conductor material is electroplated filling the trenches. The ECP process continues until the trenches in the dielectric are filled, and then overfilled, with the conductor material. This is referred to as an “overburden”.
CMP is then used to remove the overburden conductor material from the substrate surface until the upper surface of the dielectric layer is exposed between the trenches, and the patterned conductors then remain in the trenches within the dielectric layer. This ECP and CMP process is performed for each metal layer formed over the substrate.
Following the ECP and CMP processes, a uniform conductor thickness is desired with a planar upper surface. However, in actual practice the thickness uniformity of the conductor material following the ECP process (post-ECP) varies across the semiconductor substrate. The thickness of the ECP plated conductor layer is known to be affected by the conductor pattern being formed (pattern density). The pattern density causes non-uniform current density during plating, resulting in areas where the post-ECP thickness is higher than in other areas. When this higher thickness area is observed in a post-ECP inspection of the conductor material on the substrate, it is often called a “hump.”
In semiconductor processing, the post-ECP and post-CMP results are examined using “hump data” maps of semiconductor wafers. The post-ECP hump data map illustrates areas on a semiconductor substrate that have non-uniform thickness in the conductor layer after the ECP (that is, the hump data map provides a visual representation of where the “humps” occur in the conductor thickness). Hump data maps may also be used after CMP processes (referred to as post-CMP hump data maps) to identify areas where the surface of the planarized dielectric and conductor material is non-uniform after CMP.
Recently computer simulation models for both the ECP and CMP processes have been developed. These simulators are referred to herein as virtual ECP (V-ECP) and virtual CMP (V-CMP). However, the predicted hump data maps obtained using the existing V-ECP simulators do not accurately track the actual post-ECP results obtained.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the illustrative embodiments and are not necessarily drawn to scale.